The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2003

Filed:

Apr. 09, 2001
Applicant:
Inventor:

Yukimasa Ishida, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/904 ;
U.S. Cl.
CPC ...
H01L 2/904 ;
Abstract

Semiconductor islands are formed on an insulating substrate. A gate insulating layer is formed to traverse an intermediate region of each island, and a gate electrode with tapered sidewalls is formed thereon to leave wing-shaped gate insulating layer exposed at both sides. Ion implantation is done to form heavily doped regions in the semiconductor islands outside the gate insulating layers, and lightly doped drain regions under the wing regions of the gate insulating layer. An interlayer insulating layer is formed thereon to cover the gate electrodes, gate insulating layers, and the semiconductor islands. However, if the gate electrode layer and gate insulating film are patterned in the same shape, a step becomes high. If the wiring area is made narrow, the gate electrode


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Ishida, Yukimasa. (2003). Thin film transistor matrix having tft with ldd regions (U.S. Patent No. 6534789). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6534789

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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