Trench-gate semiconductor devices and their manufacture

Abstract

Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers ( ) in different ways. The trench-gate ( ) is accommodated in a narrow trench ( ) that is etched via a narrow window ( ) defined by the spacers ( ) at sidewalls of a wider window ( ) of a mask ( ) at the body surface ( ). The spacers ( ) permit a source region ( ) adjacent to the trench-gate ( ) and an insulating overlayer ( ) over the trench-gate ( ) to be self-aligned to this narrow trench ( ). The overlayer ( ), which defines a contact window ( ) for a source electrode ( ), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers ( ). Its overlap (y , y ′) with the body surface ( ) is well-defined, so reducing a short-circuit risk between the source electrode ( ) and the trench-gate ( ). Furthermore, implantation of the source region ( ) is facilitated, and a channel-accommodating region ( ) can also be provided using a high energy implant ( ) after providing the insulating overlayer ( ).