The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2003

Filed:

May. 08, 2001
Applicant:
Inventor:

Kang Rim Choi, Cupertino, CA (US);

Assignee:

Ixys Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/148 ;
U.S. Cl.
CPC ...
H01L 2/148 ;
Abstract

A packaged power semiconductor device ( ) with voltage isolation between a metal backside ( ) and the terminals ( ) of the device. A direct-bonded copper (“DBC”) substrate ( ) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die ( ) is soldered or otherwise mounted to a first metal layer ( ) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.


Find Patent Forward Citations

Choi, Kang. (2003). Method of making electrically isolated power semiconductor package (U.S. Patent No. 6534343). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6534343

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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