The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2003
Filed:
Dec. 29, 2000
David G. Figueroa, Mesa, AZ (US);
Kishore K. Chakravorty, San Jose, CA (US);
Huong T. Do, Scottsdale, AZ (US);
Larry Eugene Mosley, Sunnyvale, CA (US);
Jorge Pedro Rodriguez, Chandler, AZ (US);
Ken Brown, Mesa, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A capacitor includes multiple tiers ( , FIGS. ), which provide capacitance to a load at different inductance values. Each tier includes multiple layers ( , FIGS. ) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias ( , FIGS. ) that extend through some or all of the tiers. In another embodiment, one or more tiers ( , FIG. ) are located in a center region ( , FIG. ) of the capacitor, and one or more other tiers ( , FIG. ) are located in a peripheral region ( , FIG. ) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers ( , FIG. ) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.