The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2003
Filed:
Sep. 22, 2000
Toshiyuki Kaeriyama, Ibaraki-Ken, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of fabricating a DRAM integrated circuit structure ( ) and the structure so formed, in which a common interconnect material ( ) is used as a first level interconnection layer in both an array portion ( ) and periphery portion ( ) is disclosed. The interconnect material ( ) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal ( ) in a nitrogen ambient. Titanium silicide ( ) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates ( ) and the capacitor dielectric ( ) are formed over the interconnect material ( ), due to the thermal stability of the material. Alternative processes of forming the interconnect material ( ) are disclosed, to improve step coverage.