The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2003
Filed:
Dec. 17, 1998
Derryl D. J. Allman, Colorado Springs, CO (US);
John W. Gregory, Colorado Springs, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material. In addition a polysilicon stop layer may be exposed to a thermal cycle and oxidized into silicon dioxide after some degree of planarization to further regulate chemical mechanical polishing.