Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same

Abstract

Clock generating circuits for a semiconductor memory device are provided. The clock generating circuits include a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device. A control circuit activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self refresh mode, in which the DLL circuit is deactivated, to a standby mode. The control circuit may also be configured to deactivate the DLL circuit when the semiconductor memory device transitions from a power down mode, in which the DLL circuit is activated, to the standby mode. The semiconductor memory device may be a dynamic random access memory device and the predetermined time may be a number of clock cycles of the internal clock signal. Methods for operating the same are also provided.