The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2003
Filed:
Nov. 21, 2001
Applicant:
Inventors:
Douglas J. Cutter, Fort Collins, CO (US);
Fan Ho, Sunnyvale, CA (US);
Kurt D. Beigel, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/900 ;
U.S. Cl.
CPC ...
H01L 2/900 ;
Abstract
A method and apparatus for forming a junctionless antifuse semiconductor structure comprises forming an antifuse in non-active areas of a semiconductor wafer. In one embodiment, the antifuse is formed over a polysilicon layer, which is coupled to a field oxide layer. In a further embodiment, the polysilicon layer comprises a bottom conductor layer in the antifuse. In another embodiment, a refractory metal silicide layer is formed between the polysilicon layer and the antifuse. In yet a further embodiment, the refractory metal silicide layer comprises the bottom conductor layer in the antifuse.