The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2003
Filed:
Sep. 28, 2001
Fumio Ootsuka, Tokorozawa, JP;
Takahiro Onai, Ome, JP;
Kazuhiro Ohnishi, Kodaira, JP;
Shoji Wakahara, Yokohama, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A method of manufacture of a semiconductor device calls for forming, all over the surface of a substrate below the channel region of a MISFET, a p type impurity layer having a first peak in impurity concentration distribution and another p type impurity layer having a second peak in impurity concentration distribution, each layer having a function of preventing punch-through. Compared with a device having a punch through stopper layer with a pocket structure, the device produced by the present method operates in such a way that fluctuations in the threshold voltage are suppressed. Moreover, with a relative increase in the controllable width of a depletion layer, the sub-threshold swing becomes small, thereby making it possible to prevent lowering of the threshold voltage and to improve the switching rate of the MISFET.