The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2003
Filed:
May. 26, 2000
Applicant:
Inventors:
Prasanna Venkat Srinivas, Cupertino, CA (US);
Manjit Borah, Cupertino, CA (US);
Premal Buch, Cupertino, CA (US);
Assignee:
Magma Design Automation, Inc., Cupertino, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 ; H03K 1/9173 ; H03K 1/9177 ; G01R 3/126 ;
U.S. Cl.
CPC ...
G06F 9/45 ; H03K 1/9173 ; H03K 1/9177 ; G01R 3/126 ;
Abstract
A system for calculating interconnect wire lateral capacitances in an automated integrated circuit design system subdivides the chip area of a circuit design to be placed and routed into a coarse grid of buckets. An estimate of congestion in each bucket is computed from an estimated amount of routing space available in the bucket and estimated consumption of routing resources by a global router. This congestion score is then used to determine the spacing of the wires in the bucket which is in turn used to estimate the capacitance of the wire segment in the bucket.