The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2003

Filed:

Sep. 29, 2000
Applicant:
Inventors:

Suketu A. Parikh, Santa Clara, CA (US);

Mehul B. Naik, San Jose, CA (US);

Samuel Broydo, Los Altos Hills, CA (US);

H. Peter W. Hey, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03C 5/00 ;
U.S. Cl.
CPC ...
G03C 5/00 ;
Abstract

The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures ( and ) are formed in consecutive dielectric layers ( and ) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask ( ) upon exposure to radiation. In additional embodiments, manufacturing systems ( ) are provided for fabricating IC structures. These systems include a controller ( ) which is adapted for interacting with a plurality of fabrication stations ( and ).


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