The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2003
Filed:
Apr. 22, 1999
Won Sub Kim, Fremont, CA (US);
Mary Lynn Meyer, Mountain View, CA (US);
Daniel Marcos Chapiro, Palo Alto, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables. The method “constraint_mode” can be used to turn ON or OFF any constraint blocks of an instance.