The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2003

Filed:

Jul. 11, 2001
Applicant:
Inventors:

Sadanand V. Deshpande, Fishkill, NY (US);

Bruce B. Doris, Brewster, NY (US);

Rajarao Jammy, Wappingers Falls, NY (US);

William H. Ma, Fishkill, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/976 ;
Abstract

Divot fill methods of incorporating thin SiO spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.


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