The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2003
Filed:
May. 28, 1997
Applicant:
Inventor:
Ronald T. Taylor, Grapevine, TX (US);
Assignee:
Cirrus Logic, Inc., Austin, US;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract
A memory system includes a first array and a second array of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate ( ) interposed between column decoders ( and ) corresponding to the two memory arrays, data may be transferred between the two arrays in a single timing cycle. Furthermore, even given the interconnection between the two memory arrays due to the transfer gate, the two memory arrays can be operated independently of one another, with respect to address, data, and timing information.
Published as: