The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6509243 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 21, 2003

Filed:

Jun. 25, 2001
Applicant:
Inventor:

Yung-Chieh Fan, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1331 ;
U.S. Cl.
CPC ...
H01L 2/1331 ;
Abstract

In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a patterned insulating layer that exposes the first and second isolation regions. A patterned photoresist, formed over the substrate, exposes a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region and a trench are respectively formed in the substrate under the exposed portion of the patterned insulating layer and in the exposed portion of the second isolation region. The patterned photoresist and the patterned insulating layer are subsequently removed. First and second gate structures are respectively formed in the high-voltage and low-voltage device regions by using the trench as an alignment mark.


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Fan, Yung-Chieh. (2003). Method for integrating high-voltage device and low-voltage device (U.S. Patent No. 6509243). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6509243

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