Wide input programmable logic system and method

Abstract

A wide input programmable logic system includes a plurality of logic gates that receive a plurality of row driver signals and memory cell outputs to generate a plurality of logical NOR or NAND outputs for their respective one of said row driver signals and memory cell outputs that are programmed. At least one additional stage of logic gates having a plurality of logical NAND or NOR gates receive the respective logical NOR or NAND outputs and generate a plurality of respective logical NAND or NOR outputs. At least one respective logical NOR or NAND gate receives the respective plurality of logical NAND or NOR outputs and generates an output term. The memory cell may include an electrically erasable non-volatile memory cell having a storage cell that stores a logical value and a select transistor coupled to the storage cell. The select transistor is controlled by a first control signal, with the select transistor isolating the storage cell during editing upon receipt of an asserted state of the first control signal. A latch is coupled to the select transistor and controlled by a latch control signal to provide an output corresponding to the logical value stored in the storage cell. Respective timing of the first control signal and the latch control signal results in zero power dissipated by the electrically erasable non-volatile memory cell.