The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2003
Filed:
Feb. 29, 2000
Thomas Skotnicki, Crolles Montfort, FR;
Jérôme Alieu, Isle D'Abeau, FR;
STMicroelectronics S.A., Gentilly, FR;
Abstract
An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si Ge alloy into which indium is implanted, with 10 ≦x≦4×10 . A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si Ge alloy layer, in which 10 ≦x≦4×10 , and an external silicon layer. Indium is implanted into the Si Ge alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si Ge alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided. Germanium is implanted into at least one region of a silicon substrate where a channel region of a transistor is to be formed, in order to form a buried layer of an Si Ge alloy in which 10 ≦x≦4×10 . Indium is implanted into the Si Ge alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si Ge alloy layer.