The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2003

Filed:

Dec. 27, 2001
Applicant:
Inventors:

Dae Gyu Park, Kyungki-Do, KR;

Tae Ho Cha, Kyungki-Do, KR;

Se Aug Jang, Kyungki-Do, KR;

Heung Jae Cho, Kyungki-Do, KR;

Tae Kyun Kim, Kyungki-Do, KR;

Kwan Yong Lim, Kyungki-Do, KR;

In Seok Yeo, Seoul, KR;

Jin Won Park, Chungcheongbuk-Do, KR;

Assignee:

Hynix Semiconductor Inc, Kyoungki-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (Ti Al ) N film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (Ti Al ) N film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.


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