The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2003
Filed:
Dec. 19, 2001
Scott D. Luning, Austin, TX (US);
Jon D. Cheek, Round Rock, TX (US);
Daniel Kadosh, Austin, TX (US);
James F. Buller, Austin, TX (US);
David E. Brown, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.