The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2003

Filed:

Oct. 28, 1999
Applicant:
Inventor:

William Schwarz, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/100 ;
U.S. Cl.
CPC ...
G06F 1/100 ;
Abstract

A fast method and apparatus for built-in self-repair (BISR) of memory arrays is disclosed. In one embodiment, an integrated circuit includes a repair circuit coupled between the address decoder and the memory array. The address decoder receives memory addresses and asserts corresponding word lines. The memory array has default words associated with the word lines, but also includes extra words. By default, the repair circuit maps the word lines from the address decoder to the memory array word lines for the default words. However, the repair circuit includes at least one latch for each of the decoder word lines. When a latch is set, the repair circuit isolates the decoder word line from the default word and remaps the decoder word line to an extra word in the memory. The latches remain set while as long as power is applied, so that accesses to faulty memory words are automatically rerouted without any additional overhead relative to accesses to functional memory words. This may advantageously provide significantly reduced memory access times for only a small increase in hardware cost.


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