The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2003
Filed:
Apr. 23, 2001
Applicant:
Inventor:
Roger S. Tsai, Torrance, CA (US);
Assignee:
TRW Inc., Redondo Beach, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract
A model for a semiconductor device and more particularly to a Pi-FET with multiple gate fingers. The model takes into account various parasitics and the inter-relationship therebetween. In particular, multi-finger Pi-FETs are modeled as multiple single finger unit cells. Each single unit cell takes into account off-mesa parasitics, inter-electrode parasitics, on-mesa parasitics and includes an intrinsic model which represents the physics that predominantly determine FET performance. As such, the model can be used for relativity accurate device technology modeling, optimization of device performance and device design.