The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2002

Filed:

Apr. 21, 2000
Applicant:
Inventors:

Yoshifumi Watabe, Tondabayashi, JP;

Yukihiro Kondo, Hirakata, JP;

Koichi Aizawa, Neyagawa, JP;

Takuya Komoda, Sanda, JP;

Yoshiaki Honda, Kyoto, JP;

Takashi Hatai, Neyagawa, JP;

Tsutomu Ichihara, Hirataka, JP;

Nobuyoshi Koshida, Kodaira, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J 1/00 ; H01J 1/05 ; H01J 1/14 ; H01J 1/906 ; H01J 9/04 ;
U.S. Cl.
CPC ...
H01J 1/00 ; H01J 1/05 ; H01J 1/14 ; H01J 1/906 ; H01J 9/04 ;
Abstract

A field emission-type electron source ( ) is provided with a conductive substrate ( ), a semiconductor layer formed on a surface of the conductive substrate ( ), at least a part of the semiconductor layer being made porous, and a conductive thin film ( ) formed on the semiconductor layer. Electrons injected into the conductive substrate ( ) are emitted from the conductive thin film ( ) through the semiconductor layer by applying a voltage between the conductive thin film ( ) and the conductive substrate ( ) in such a manner that the conductive thin film ( ) acts as a positive electrode against the conductive substrate ( ). The semiconductor layer includes a porous semiconductor layer ( ) in which columnar structures ( ) and porous structures ( ) composed of fine semiconductor crystals of nanometer scale coexist, a surface of each of the structures being covered with an insulating film ( ). Further, an average dimension of each of the porous structures ( ) in a thickness direction of the semiconductor layer is smaller than or equal to 2 &mgr;m.


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