The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2002

Filed:

Dec. 11, 2000
Applicant:
Inventors:

Kozo Sakamoto, Hitachinaka, JP;

Yosuke Inoue, Tokai-mura, JP;

Akihiro Miyauchi, Hitachi, JP;

Masaki Shiraishi, Hitachi, JP;

Mutsuhiro Mori, Mito, JP;

Atsuo Watanabe, Hitachiota, JP;

Takasumi Ohyanagi, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 3/1119 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ;
U.S. Cl.
CPC ...
H01L 3/1119 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ;
Abstract

In a semiconductor device having a first terminal (source terminal) and a second terminal (drain terminal), the substrate main surface of a semiconductor chip is on the ( ) face, the main contact face of an n-type region and a p-type region is the { } face perpendicular to the ( ) face, elongated n-type regions and elongated p-type regions , which are arranged alternately, form a voltage holding area. The first terminal is connected to the p-type regions through wiring, and the second terminal is connected to the n-type regions . Also, the p-type region is formed to cover the bottom comers of a gate polycrystalline silicon layer


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