The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2002
Filed:
May. 24, 2000
Andres Bryant, Essex Junction, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Minh H. Tong, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10 Ohms−um divided by the width of the pass-gate.