Method and system for circuit design top level and block optimization

Abstract

In a computer-implemented synthesis system, a method of optimizing a design of an integrated circuit device. The optimization process includes the computer-implemented steps of accessing a circuit netlist representing an integrated circuit design to be realized in physical form, wherein the circuit netlist includes a top-level block and at least a first and a second circuit block. The top-level block includes glue logic for coupling the first and second circuit blocks. The process creates a first model of the first circuit block and a second model of the second circuit block, the first model and the second model each operable for independently abstracting embodying circuitry of the first and second circuit blocks, respectively. The circuit netlist is optimized by independently optimizing the first circuit block and the second circuit block, and the top-level block to yield a fully optimized circuit netlist. The first and second circuit blocks are both independently optimized. Then, the first and second circuit blocks within the top-level block are replaced with the first and second models respectively. The top-level block is then optimized with the first and second models included therein, thereby reducing the computer resources required to optimize the top-level block. Subsequently, a fully optimized circuit netlist is generated by combining the optimized first and second circuit blocks with the optimized top-level block.