The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Mar. 27, 2001
Wenyi Feng, Allentown, PA (US);
William A. Oswald, Allentown, PA (US);
Michael L. Roy, Westminster, CO (US);
Eric Ting, Allentown, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A programming tool for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), supports the display of hidden-switch connections, in addition to the display of conventional placed-switch, switch-box, and pseudo-arc connections. A hidden-switch connection between two functional elements in the PLD is represented in graphical displays generated by the programming tool as a curve (e.g., a diagonal straight line) from a jumper wire on the first functional element to another jumper wire on the second functional element, where a jumper wire is represented in the graphical display as a wire connected at one end to an pin of the corresponding functional element and unconnected at the other end. A programming tool that supports hidden-switch connections can be used to program FPGAs and other PLDs having architectures that were not previously supported by conventional programming tools that do not support hidden-switch connections.