Step-down clock control and method for improving convergence for a digitally controlled self-calibrating vco

Abstract

A PLL system ( ) includes a clock sequence generator ( ). Clock sequence generator ( ) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter ( ) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD ( ) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit ( ) and the signals UP and DOWN are supplied to the counter ( ). The counter ( ) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system ( ) is accelerated by the effects of the step-down clock provided by the clock sequence generator ( ).