The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Aug. 09, 2001
Chuan-Cheng Cheng, Fremont, CA (US);
Yauh-Ching Liu, Sunnyvale, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step. The second capacitor plate and the fuse may be defined simultaneously by selectively removing portions of the conductive layer during a single etching step. Thus, the invention provides for forming various structures of the capacitor and the fuse during the same photomask, patterning, and etching steps, thereby reducing fabrication cost and time.