The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2002
Filed:
Sep. 27, 2000
Shafqat Ahmed, Beaverton, OR (US);
Hemanshu D. Bhatt, Troutdale, OR (US);
Robindranath Banerjee, Gresham, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices.