The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Mar. 31, 1999
Won Sub Kim, Fremont, CA (US);
Valeria Maria Bertacco, Stanford, CA (US);
Daniel Marcos Chapiro, Palo Alto, CA (US);
Sandro Hermann Pintz, Menlo Park, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an “expect,” for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance. In particular, upon the first occurrence of a transition on one of the DUT's nodes, since beginning a window period of monitoring, the expect will either generate an error if the DUT's output is unexpected, or proceed with modeling the DUT's environment if the output is expected. A delay may be specified, which will delay the expect's initiation of the window monitoring period.