The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2002
Filed:
Nov. 17, 2000
Susumu Akamatsu, Osaka, JP;
Toshitaka Hibi, Kyoto, JP;
Takehiko Ueda, Kyoto, JP;
Tadami Shimizu, Osaka, JP;
Yoshiaki Kato, Hyogo, JP;
Tatsuya Obata, Toyama, JP;
Toyoyuki Shimazaki, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in. Accordingly, it is possible to provide a method for fabricating a semiconductor device contributing to device miniaturization without causing a shortcircuit between the gate electrode and a contact member.