The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2002

Filed:

Dec. 26, 2000
Applicant:
Inventors:

Louis Chao-Chiuan Liu, Hsin-Chu, TW;

Chien-Wen Chen, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/182 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/182 ; H01L 2/14763 ;
Abstract

A structure and a method for forming cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment the driver is formed in a micro cell. A signal line is connected to the pin and the driver.


Find Patent Forward Citations

Quick Actions:

Liu, Louis Chao-Chiuan. (2002). Utilization of macro power routing area for buffer insertion (U.S. Patent No. 6492205). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6492205

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…