The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2002

Filed:

Feb. 09, 2001
Applicant:
Inventors:

Thomas Gehrke, Carrboro, NC (US);

Kevin J. Linthicum, Angier, NC (US);

Robert F. Davis, Raleigh, NC (US);

Darren B. Thomson, Cary, NC (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/120 ;
U.S. Cl.
CPC ...
H01L 2/120 ;
Abstract

Embodiments of the present invention pendeoepitaxially grow sidewalls of posts in an underlying gallium nitride layer that itself is on a sapphire substrate, at high temperatures between about 1000° C. and about 1100° C. and preferably at about 1100° to reduce vertical growth of gallium nitride on the trench floor from interfering with the pendeoepitaxial growth of the gallium nitride sidewalls of the posts. Thus, widely available sapphire substrates may be used for pendeoepitaxial of gallium nitride, to thereby allow reduced cost and/or wider applications for gallium nitride devices. More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer.


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