The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2002

Filed:

May. 19, 2000
Applicant:
Inventors:

George Conner, Los Gatos, CA (US);

Peter Reichert, Thousand Oaks, CA (US);

Assignee:

Teradyne, Inc., Boston, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/126 ;
U.S. Cl.
CPC ...
G01R 3/126 ;
Abstract

An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through coaxial cables. The test system includes a buffer amplifier on a device interface board to fan out the DATA CLOCK generated by the device under test to that channel circuitry. The interconnection between the buffer amplifier and the channel circuitry is provided through a coax with low dielectric constant, to compensate for the delay introduced by the buffer amplifier.


Find Patent Forward Citations

Conner, George. (2002). Method and apparatus for testing integrated circuit chips that output clocks for timing (U.S. Patent No. 6486693). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6486693

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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