The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2002

Filed:

Nov. 22, 2000
Applicant:
Inventors:

Jong-soo Lee, Kyungki-do, KR;

Kye-hyun Kyung, Kyungki-do, KR;

Dae-sun Kim, Kyungki-do, KR;

Hyo-jin Oh, Kyungki-do, KR;

Sang-chul Kim, Kyungki-do, KR;

Tae-seek Son, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 2/312 ;
U.S. Cl.
CPC ...
G01R 2/312 ;
Abstract

Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.


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