The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2002
Filed:
Dec. 10, 2001
Yen-hung Yeh, Taoyuan Hsien, TW;
Tso-Hung Fan, Taipei Hsien, TW;
Mu Yi Liu, Taichung, TW;
Kwang Yang Chan, Hsinchu, TW;
Tao-Cheng Lu, Kaoshiung, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
A method of scaling down device dimension using spacer to confine the buried drain implant, applicable for forming memory device such as substrate/oxide/nitride/oxide/silicon (SONOS) stacked device or nitride read only memory (NROM) device. A patterned conductive layer is used as a mask for forming a pocket doped region. A spacer is formed on a side-wall of the conductive layer. As the implantation region is confined by the side-wall, a buried drain region formed by drain implantation is reduced. Therefore, the effective channel length is not reduced due to the diffusion of the buried drain region. It is thus advantageous to scale down device dimension.