The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2002

Filed:

Feb. 08, 1999
Applicant:
Inventors:

Robert F. Molyneaux, Lakeway, TX (US);

Rajesh Raina, Austin, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/900 ;
U.S. Cl.
CPC ...
G06F 1/900 ;
Abstract

The invention is a method and apparatus that verifies the design of electronic circuitry containing a function to be tested. An input, such as a random input, is provided to the electronic circuitry containing the function, yielding an output. This output, in turn, is used as input (denominated “inverse input”) to an inverse of the function to be tested. The resulting output (termed “inverse output”) is compared to the original input to the function to be tested to facilitate verification of the design of the circuitry.


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Molyneaux, Robert. (2002). Method and system for generating self-testing and random input stimuli for testing digital systems (U.S. Patent No. 6480800). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6480800

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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