The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
Feb. 01, 2002
David E. Jefferson, San Jose, CA (US);
Cameron McClintock, Mountain View, CA (US);
James Schleicher, Santa Clara, CA (US);
Andy L. Lee, San Jose, CA (US);
Manuel Mejia, San Jose, CA (US);
Bruce B. Pederson, San Jose, CA (US);
Christopher F. Lane, Campbell, CA (US);
Richard G. Cliff, Milpitas, CA (US);
Srinivas T. Reddy, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.