The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2002
Filed:
Dec. 28, 1998
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source V for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.