Reduced masking step cmos transistor formation using removable amorphous silicon sidewall spacers

Abstract

CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.