The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2002
Filed:
Nov. 03, 1999
James Vernon Rhodes, Chandler, AZ (US);
Robert David Conklin, Chandler, AZ (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in response, this memory sends a corresponding series of translated addresses to a memory output. Multiple output registers are coupled to the memory output, and each output register stores a respective translated address in the series. With this intermediate stage, the input addresses can be virtual addresses in a virtual, or hypothetical, memory; and, those virtual addresses can be translated into physical addresses for an actual memory chip that is to be tested.