Field effect transistor with barrier layer to prevent avalanche breakdown current from reaching gate and method for manufacturing the same

Abstract

A p-type layer and an n-type layer which constitute a barrier layer are provided, and a leak of the holes at the time of the negative bias accompanying the p-type layer buffer required for the higher tolerance voltage is suppressed, and the discharge of the holes at the positive bias can be efficiently carried out. The tolerance voltage at the time of the OFF state is raised at the p-type layer buffer, and the tolerance voltage at the time of the ON state at the discharge of the holes is raised. Since no leak is generated from the p-type layer, the drain current is not lowered, and a higher output can be realized both in terms of the current and in terms of the voltage.