The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2002

Filed:

Nov. 12, 1999
Applicant:
Inventors:

Yasuo Ohno, Tokyo, JP;

Kensuke Kasahara, Tokyo, JP;

Kazuaki Kunihiro, Tokyo, JP;

Yuji Takahashi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/980 ; H01L 3/10328 ; H01L 3/10336 ; H01L 3/1072 ; H01L 3/1112 ;
U.S. Cl.
CPC ...
H01L 2/980 ; H01L 3/10328 ; H01L 3/10336 ; H01L 3/1072 ; H01L 3/1112 ;
Abstract

A p-type layer and an n-type layer which constitute a barrier layer are provided, and a leak of the holes at the time of the negative bias accompanying the p-type layer buffer required for the higher tolerance voltage is suppressed, and the discharge of the holes at the positive bias can be efficiently carried out. The tolerance voltage at the time of the OFF state is raised at the p-type layer buffer, and the tolerance voltage at the time of the ON state at the discharge of the holes is raised. Since no leak is generated from the p-type layer, the drain current is not lowered, and a higher output can be realized both in terms of the current and in terms of the voltage.


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