Gate contact etch sequence and plasma doping method for sub-150 nm dt-based dram devices

Abstract

An improved etch sequence and an improved integration scheme of plasma doping in the fabrication of a DRAM integrated circuit device are described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an array area and a periphery area. The semiconductor device structures are covered with a dielectric layer. The dielectric layer is concurrently etched through in the array area to form bit line contact openings and in the periphery area to form substrate contact openings. Doped regions are formed in the substrate exposed within the bit line contact openings and the substrate contact openings using a plasma doping process. Next, the dielectric layer is etched through to form a gate contact opening. Thereafter, the bit line contact openings, the substrate contact openings, and the gate contact opening are filled with a conducting layer to complete forming contacts in the fabrication of a DRAM integrated circuit.