Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier

Abstract

Circuitry and method for effectuating low power read operations in a memory circuit, e.g., a memory instance having a banked architecture. When a memory read cycle is initiated with respect to a particular memory cell in a selected bank based on a plurality of address signals, a specific wordline associated with the memory cell is driven high. Upon waiting until the bitline coupled thereto reach a predetermined sense level, the wordline is shut off based on a reference memory cell structure, which wordline thereby stops driving the bitline. Subsequently, after waiting for a select time, the sense amplifier senses the data stored in the particular memory cell based a charge distribution between its internal node(s) and the bitline after the selected wordline is deactivated.