The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2002

Filed:

Apr. 21, 2000
Applicant:
Inventors:

Keng-Chia Yang, Chang-Hua, TW;

Yo Chang, Hsin-Chu, TW;

Chen-Lung Chu, Hsin-Chu, TW;

Yi-Hung Lee, Yung-Ho, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/900 ;
U.S. Cl.
CPC ...
G06F 1/900 ;
Abstract

The invention is proposed to efficiently dispatch wafers into tools, and particularly to provide a real-time and automatic way to dispatch wafers. In addition, a method for dispatching wafers, a system for dispatching wafers into tools and a system for processing numerous lots by number of tools with automatic dispatch are present as examples. One main characteristic of the invention is that each pending wafer is given an individual priority before it is processed by any tool and the priority is automatically calculated in accordance with to a ranking algorithm. Another main characteristic of the invention is that whenever a tool is available to process at least one pending wafer, part of pending wafers is automatically assigned to the available tool in accordance with an assignment algorithm and a required limitation database that is provided by the dispatcher. In the ranking algorithm, each priority is a summation of following terms: Q-Time term, waiting status term, commit due date term, output term, hot run priority, idle term, super hot run term and exception rule term. Herein, these priorities are adjusted by some system variables that modified by dispatcher. In the lot assignment algorithm, each wafer is dispatched to an available tool in accordance with following restriction: scheduled output must be satisfied, output of each tool must be maximized and wafer with higher priority must be preferentially processed. Moreover, exigency of wafers includes super hot run, hot run and normal run, and each exigency corresponds to an individual dispatching flow.


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Yang, Keng-Chia. (2002). Method and system for auto dispatching wafer (U.S. Patent No. 6470231). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6470231

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