The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2002

Filed:

Apr. 10, 2001
Applicant:
Inventors:

Shinichi Muramatsu, Tokyo, JP;

Harunori Sakaguchi, Tsuchiura, JP;

Susumu Takahashi, Abiko, JP;

Assignee:

Hitachi Cable, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ; H01L 2/184 ; H01L 2/104 ;
U.S. Cl.
CPC ...
H01L 2/100 ; H01L 2/184 ; H01L 2/104 ;
Abstract

At least a part of the surface of a crystalline silicon semiconductor substrate is rendered porous to convert at least a part of the crystalline silicon semiconductor substrate to a porous silicon layer. A catalytic metal layer is formed on the porous silicon layer. An amorphous silicon thin film is formed on the catalytic metal layer. The amorphous silicon thin film is heated to monocrystallize the amorphous silicon thin film, thereby converting the amorphous silicon thin film to a crystalline silicon thin film. The crystalline silicon semiconductor substrate, provided with the crystalline silicon thin film, is joined to a support substrate so that the crystalline silicon thin film faces the support substrate. The crystalline silicon semiconductor substrate, together with the porous silicon layer, which is the crystalline silicon semiconductor substrate in its portion converted to a porous layer, is separated and removed from the crystalline silicon thin film joined to the support substrate. By virtue of the above constitution, a process for producing a crystalline silicon thin film can be realized which enables, for example, the temperature required in the production process of a crystalline silicon thin film to be lowered to improve the quality of the crystalline silicon thin film, can realize close control of a steep dopant concentration gradient and the like, and can produce a crystalline silicon thin film suitable for an increase in fabrication density and a reduction in layer thickness of semiconductor devices.


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