The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6465867 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 15, 2002

Filed:

Feb. 21, 2001
Applicant:
Inventors:

Joffre F. Bernard, Redwood City, CA (US);

Sergey D. Lopatin, Santa Clara, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/900 ;
U.S. Cl.
CPC ...
H01L 2/900 ;
Abstract

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.


Find Patent Forward Citations

Bernard, Joffre. (2002). Amorphous and gradated barrier layer for integrated circuit interconnects (U.S. Patent No. 6465867). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6465867

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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