Surrounding-gate flash memory having a self-aligned control gate

Abstract

The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the device isolation structures and on the substrate where the sources are present. Drains are provided in the top layer of the substrate where the tunneling oxide layer is absent in between the device isolation structures. Polysilicon blocks are extended across the ends of two device isolating structures, above the tunnel oxide layer. A silicon oxide cap layer is located on the polysilicon block. The silicon oxide layers are formed on the sidewalls of the polysilicon blocks. The polysilicon layer is on the sidewall of the polysilicon blocks and the polysilicon blocks are separated by the silicon oxide layer. The silicon oxide layer covers the surface of the polysilicon layers. Another polysilicon layer, which is located on the tunnel silicon oxide layer above the sources also, covers a part of the silicon oxide cap layer.