The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2002

Filed:

Sep. 05, 2000
Applicant:
Inventors:

Chyh-Yih Chang, Taipei Hsien, TW;

Ming-Dou Ker, Hsinchu, TW;

Hsin-Chin Jiang, Taipei, TW;

Jeng-Jie Peng, Tau-Yun, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1332 ; H01L 2/18238 ; H01L 2/974 ; H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/1332 ; H01L 2/18238 ; H01L 2/974 ; H01L 2/976 ;
Abstract

A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.


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