The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2002
Filed:
Jan. 16, 2001
Applicant:
Inventors:
Andy L. Lee, San Jose, CA (US);
Christopher F. Lane, San Jose, CA (US);
Srinivas T. Reddy, Fremont, CA (US);
Brian D. Johnson, Sunnyvale, CA (US);
Ketan H. Zaveri, San Jose, CA (US);
Mario Guzman, San Jose, CA (US);
Quyen Doan, Milpitas, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9177 ; H03K 1/9173 ;
U.S. Cl.
CPC ...
H03K 1/9177 ; H03K 1/9173 ;
Abstract
A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.